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Setup and Operation
1.2.14
Prototyping Area
A 0.1" pitch prototyping area is provided on the board.
Digital (V DD /V SS ) and analog (AV DD /AV SS ) power supplies are provided in the four
corners.
J6 provides access to all the ADC channels as well as having unassigned analog
signals on it.
J7 provides access to any optional or unassigned digital I/O pins.
1.3
INTERFACE VIA THE 37-PIN CONNECTOR - J1
1.3.1
Introduction
The 37-pin, D-type connector (J1) and the associated signal routing and circuitry have
been designed to directly interface with one of the custom power modules that are
available. These complement this board by removing the need for the user to have their
own power stage. The power modules contain all the necessary driving circuitry, have
robust FAULT protection and many different feedback signals. For details as to the
interfacing requirements, feedback scaling and power capabilities for the particular
power module, the user should consult the power module documentation.
Due to the finite number of ADC channels and the fact that some of the pins are shared
with other modules, it is not possible to connect all of the power module feedback
signals to the ADC module at the same time.
In general, up to four phase motors have been allowed for in terms of firing signals and
feedback information. Given that 4-phase motors are not all that common, where
compromises were needed owing to ADC or input pin restriction, 3-phase motors have
been given preference.
A small amount of RC filtering is used on all the analog feedback signals for ESD
protection and noise suppression. The resistors have been chosen to have minimal
impact on ADC acquisition time.
1.3.2
Switch Firing Commands
A total of ten PWM signals are routed to the 37-pin connector via high current 74AC244
buffers. The output of the buffers directly drives the LEDs of the optocouplers, as well
as LEDs that are visible through the front of the enclosure of the power module.
Note:
The 74AC244 buffers are not required in most designs. The dsPIC PWM
pins can drive most gate drive circuitry directly. Refer to the device data
sheet for further details. The buffers provide protection of the dsPIC I/O pins
in a development environment and provide drive strength for the loads
presented by the power module interface circuitry.
In order to ensure correct operation of the firing signal outputs via J1 when the inputs
to the buffers are tri-stated, an overall active low FIRE_ENABLE control line is used via
RD11. The FIRE_ENABLE line is pulled up via R14 and must be pulled low by the
user's software to enable the buffers.
Eight of the firing commands come from the Motor Control PWM module. Of these
eight, two are optional owing to the limited number of pins on the connector. These are
the Phase#4 firing commands. They are shared with two of the back EMF crossing
signals. As delivered, the board is configured to use the back EMF crossing signals –
LK4 and LK5 are fitted in position 2-3.
Two of the firing commands used for the brake chopper and PFC come from output
compare channels 5 and 6. These channels should be configured in the PWM mode
with the FAULT pin enabled.
? 2003 Microchip Technology Inc.
DS70098A-page 9
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